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FPGA
The semiconductor FAB market is an exciting place to be, fast paced, data and results driven, detail oriented, constantly striving to improve and always looking for lower cost solutions. Semiconductors are vital technology and their importance to the world’s economy and SEMICONDUCTOR BOOM IN 2021 The third quarter 2020 semiconductor market totaled $114 billion, up 11.0% from second quarter 2020, according to World Semiconductor Trade Statistics (WSTS). The 3Q20 growth was the highest since 11.6% in 3Q16. The strong 3Q20 growth follows a 2.1% decline in 2Q20 versus 1Q20. The second quarter is normally a healthy growth quarter,averaging 4%
PCI EXPRESS IN DEPTH In the last article i write about the Data Link Layer, in this article i'll write about the Transaction Layer. This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. The Transaction Layer uses TLPs to communicate request and completion THE 10 HOTTEST SEMICONDUCTOR STARTUPS OF 2020 Nov 25, 2020. #1. According to CRN: Ampere Computing. CEO: Renee James. Founded and led by former Intel executive Renee James, Ampere Computing is building Arm-based server CPUs with a focus on high-performance, power efficiency and total cost of ownership. The Santa Clara, Calif.-based startup revealed two processors this year:the 80-core
ALPHAWAVE WIKI
Alphawave is a team of technology industry veterans and engineers with a nearly 20 year history of building successful Silicon/IP teams. Founded in 2017, Alphawave has already seen strong success and impact in delivering proven Silicon in leading 7nm processes. Profitable since day one, Alphawave is investing heavily in our existing andfuture
ASML EARLY SIGNS OF AN ORDER TSUNAMI Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance. ASML a tidal wave of orders On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir ULTRA-HIGH DENSITY DIRECT CONNECT TECHNOLOGY FROM SAMTEC A 5X increase in reach due to no PCB interconnect. He also goes into some details about Samtec’s next generation Direct Connect technology – Si-Fly. The low-profile, high density of this technology will deliver 25.6 TB aggregate data rate with a path top 51.2 TB in the time frames shown in the figure, below. INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely. AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next SEMIWIKI - ALL THINGS SEMICONDUCTOR!FORUMEDAIPSERVICESFOUNDRIESEFPGA /FPGA
The semiconductor FAB market is an exciting place to be, fast paced, data and results driven, detail oriented, constantly striving to improve and always looking for lower cost solutions. Semiconductors are vital technology and their importance to the world’s economy and SEMICONDUCTOR BOOM IN 2021 The third quarter 2020 semiconductor market totaled $114 billion, up 11.0% from second quarter 2020, according to World Semiconductor Trade Statistics (WSTS). The 3Q20 growth was the highest since 11.6% in 3Q16. The strong 3Q20 growth follows a 2.1% decline in 2Q20 versus 1Q20. The second quarter is normally a healthy growth quarter,averaging 4%
PCI EXPRESS IN DEPTH In the last article i write about the Data Link Layer, in this article i'll write about the Transaction Layer. This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. The Transaction Layer uses TLPs to communicate request and completion THE 10 HOTTEST SEMICONDUCTOR STARTUPS OF 2020 Nov 25, 2020. #1. According to CRN: Ampere Computing. CEO: Renee James. Founded and led by former Intel executive Renee James, Ampere Computing is building Arm-based server CPUs with a focus on high-performance, power efficiency and total cost of ownership. The Santa Clara, Calif.-based startup revealed two processors this year:the 80-core
ALPHAWAVE WIKI
Alphawave is a team of technology industry veterans and engineers with a nearly 20 year history of building successful Silicon/IP teams. Founded in 2017, Alphawave has already seen strong success and impact in delivering proven Silicon in leading 7nm processes. Profitable since day one, Alphawave is investing heavily in our existing andfuture
ASML EARLY SIGNS OF AN ORDER TSUNAMI Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance. ASML a tidal wave of orders On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir ULTRA-HIGH DENSITY DIRECT CONNECT TECHNOLOGY FROM SAMTEC A 5X increase in reach due to no PCB interconnect. He also goes into some details about Samtec’s next generation Direct Connect technology – Si-Fly. The low-profile, high density of this technology will deliver 25.6 TB aggregate data rate with a path top 51.2 TB in the time frames shown in the figure, below. INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely. AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next ASML EARLY SIGNS OF AN ORDER TSUNAMI Taiwan and Korea represented 43% and 44% respectively with China at 15% and Japan and the US in the far distance. ASML a tidal wave of orders On the call management talked about logic potentially being up 30% in 2021 and memory being up potentially 50%. While we thing foundry/logic will clearly be on fir LEADING EDGE FOUNDRY WAFER PRICES I have seen several articles recently discussing foundry wafer selling prices for leading edge wafers, these articles all quote estimates from a paper by the Center for Security and Emerging Technology (CSET). The paper is available here. My company IC Knowledge LLC is the world leader in cost and price modeling of semiconductors andMEMS.
DESIGN RULE CHECKING (DRC) MEETS NEW CHALLENGES The traditional batch-oriented DRC process run as a final check to ensure compliance with foundry yield goals is quickly moving toward a concurrent DRC process performed early and often throughout design, especially at the 28 nm and smaller process nodes. What are the technology factors causing this change? Increasing number of rules andtheir complexity
EFFICIENT HANDLING OF TIMING ECOS Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancingprocess
SAMSUNG SUCCESSFULLY COMPLETES 8NM RF SOLUTION DEVELOPMENT New 8nm RF chip architecture provides up to 35 percent increase in power efficiency and 35 percent decrease in logic area compared to 14nm RF Samsung Foundry 8nm RF process technology for 5G Sub-6GHz/mmWave Chip Designs (Graphic: Samsung) June 08, HOW INTEL LOST ITS DOMINANCE IN THE COMPUTER Last week, Intel announced its second-quarter financial results which easily beat the analysts’ consensus expectations by a handsome margin. Yet the stock price plummeted by over 16% right after the earnings call with management. Seven analysts downgraded the stock to a sell and the common theme on all the downgrades was that their7-nanometer process
LIBRARY CHARACTERIZATION: A SIEMENS CLOUD SOLUTION USING Pressing demands on compute speeds, storage capacity and rapid access to data are not new to the semiconductor industry. A desire for access to on-demand computing resources have always been there. During pre-cloud-computing era, companies provisioned on-demand compute capacity by procuring high performance computing equipment that could handle peak demand. This led to under-utilization of IP WARS ARE HERE AND NOW IP wars are here and now and it's time to wake up and take them seriously. Everything from building chips to hacking IP is part of this war and make no mistake about it, it has become a war in numerous fields with numerous fronts. The IP that can be put on a single thumbdrive can be worth
SEMIWIKI.COM
semiwiki.com
TSMC CONSIDERING FIRST CHIP PACKAGING PLANT IN US Search titles only. By: Search Advanced search SEMIWIKI - ALL THINGS SEMICONDUCTOR!FORUMEDAIPSERVICESFOUNDRIESEFPGA /FPGA
The semiconductor FAB market is an exciting place to be, fast paced, data and results driven, detail oriented, constantly striving to improve and always looking for lower cost solutions. Semiconductors are vital technology and their importance to the world’s economy and SPIE 2021 – APPLIED MATERIALS – DRAM SCALING At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed. I also spoke to Regina Freed last year afterSPIE
7NM, 5NM AND 3NM LOGIC, CURRENT AND PROJECTED PROCESSES There has been a lot of new information available about the leading-edge logic processes lately. Papers from IEDM in December 2017, VLSIT this month, the TSMC and Samsung Foundry forums, etc. have all filled in a lot of information. In this article I will summarize what is currently known. Process Metrics Standard cells are used THE 10 HOTTEST SEMICONDUCTOR STARTUPS OF 2020 Nov 25, 2020. #1. According to CRN: Ampere Computing. CEO: Renee James. Founded and led by former Intel executive Renee James, Ampere Computing is building Arm-based server CPUs with a focus on high-performance, power efficiency and total cost of ownership. The Santa Clara, Calif.-based startup revealed two processors this year:the 80-core
INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely.ALPHAWAVE WIKI
Alphawave is a team of technology industry veterans and engineers with a nearly 20 year history of building successful Silicon/IP teams. Founded in 2017, Alphawave has already seen strong success and impact in delivering proven Silicon in leading 7nm processes. Profitable since day one, Alphawave is investing heavily in our existing andfuture
A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
COST TRADEOFFS AT 28NM VS 40NM (ARM M0+) TSMC's 28nm process technology features high performance and low power consumption advantages plus seamless integration with its 28nm design ecosystem to enable faster time-to-market. The 28nm process technology supports a wide range of applications, including Central Processing Units (CPUs), graphic processors (GPUs), high-speed networking WHAT IS THE DIFFERENCE BETWEEN CCS VS NLDM VS ECSM LIBRARY Hi, I am quite uncertain about the difference between CCS, NLDM and ECSM. I will really appreciate if anyone can give the information regarding this. In addition to that, from the layout generation to tapout of design in IC compiler, which model should be used ? ThanksSachin
SEMIWIKI - ALL THINGS SEMICONDUCTOR!FORUMEDAIPSERVICESFOUNDRIESEFPGA /FPGA
The semiconductor FAB market is an exciting place to be, fast paced, data and results driven, detail oriented, constantly striving to improve and always looking for lower cost solutions. Semiconductors are vital technology and their importance to the world’s economy and SPIE 2021 – APPLIED MATERIALS – DRAM SCALING At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed. I also spoke to Regina Freed last year afterSPIE
7NM, 5NM AND 3NM LOGIC, CURRENT AND PROJECTED PROCESSES There has been a lot of new information available about the leading-edge logic processes lately. Papers from IEDM in December 2017, VLSIT this month, the TSMC and Samsung Foundry forums, etc. have all filled in a lot of information. In this article I will summarize what is currently known. Process Metrics Standard cells are used THE 10 HOTTEST SEMICONDUCTOR STARTUPS OF 2020 Nov 25, 2020. #1. According to CRN: Ampere Computing. CEO: Renee James. Founded and led by former Intel executive Renee James, Ampere Computing is building Arm-based server CPUs with a focus on high-performance, power efficiency and total cost of ownership. The Santa Clara, Calif.-based startup revealed two processors this year:the 80-core
INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely.ALPHAWAVE WIKI
Alphawave is a team of technology industry veterans and engineers with a nearly 20 year history of building successful Silicon/IP teams. Founded in 2017, Alphawave has already seen strong success and impact in delivering proven Silicon in leading 7nm processes. Profitable since day one, Alphawave is investing heavily in our existing andfuture
A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
COST TRADEOFFS AT 28NM VS 40NM (ARM M0+) TSMC's 28nm process technology features high performance and low power consumption advantages plus seamless integration with its 28nm design ecosystem to enable faster time-to-market. The 28nm process technology supports a wide range of applications, including Central Processing Units (CPUs), graphic processors (GPUs), high-speed networking WHAT IS THE DIFFERENCE BETWEEN CCS VS NLDM VS ECSM LIBRARY Hi, I am quite uncertain about the difference between CCS, NLDM and ECSM. I will really appreciate if anyone can give the information regarding this. In addition to that, from the layout generation to tapout of design in IC compiler, which model should be used ? ThanksSachin
THE 10 HOTTEST SEMICONDUCTOR STARTUPS OF 2020 Nov 25, 2020. #1. According to CRN: Ampere Computing. CEO: Renee James. Founded and led by former Intel executive Renee James, Ampere Computing is building Arm-based server CPUs with a focus on high-performance, power efficiency and total cost of ownership. The Santa Clara, Calif.-based startup revealed two processors this year:the 80-core
PCI EXPRESS IN DEPTH In the last article i write about the Data Link Layer, in this article i'll write about the Transaction Layer. This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. The Transaction Layer uses TLPs to communicate request and completion LIBRARY CHARACTERIZATION: A SIEMENS CLOUD SOLUTION USING Pressing demands on compute speeds, storage capacity and rapid access to data are not new to the semiconductor industry. A desire for access to on-demand computing resources have always been there. During pre-cloud-computing era, companies provisioned on-demand compute capacity by procuring high performance computing equipment that could handle peak demand. This led to under-utilization of APPLE’S PRIORITY ON IMPROVED OLED ENCAPSULATION FOR Smartphone shipments have been dropping over the past few years, as shown in Chart 1, as a result of several factors, but primarily the slowdown in smartphone innovation while at the same time prices have kept increasing. Even with the much anticipated 5G in 2020, unimpressive speed gains coupled with a Covid-19 backdrop, smartphonesunit
SAMSUNG SUCCESSFULLY COMPLETES 8NM RF SOLUTION DEVELOPMENT New 8nm RF chip architecture provides up to 35 percent increase in power efficiency and 35 percent decrease in logic area compared to 14nm RF Samsung Foundry 8nm RF process technology for 5G Sub-6GHz/mmWave Chip Designs (Graphic: Samsung) June 08, ENABLING NEXT GENERATION SILICON IN PACKAGE PRODUCTS In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been categorized into eight different subject matter tracks. LEADING EDGE FOUNDRY WAFER PRICES I have seen several articles recently discussing foundry wafer selling prices for leading edge wafers, these articles all quote estimates from a paper by the Center for Security and Emerging Technology (CSET). The paper is available here. My company IC Knowledge LLC is the world leader in cost and price modeling of semiconductors andMEMS.
SOC INTEGRATION
On its face System-on-chip (SoC) integration doesn’t seem so hard. You gather and configure all the intellectual properties (IPs) you’re going to need, then stitch them together. Something you could delegate to new college hires, maybe? But it isn’t that simple. What makes SoC integration challenging is that there are so many partsincluding IPs
CONFIGURATION ENVIRONMENT IS MAKE-OR-BREAK FOR IC All semiconductor design work today rests on the three-legged stool of Foundries, EDA Tools and Designers. Close collaboration between the three make possible the successful completion of ever more complex designs, especially those at advanced nodes. Perhaps one of the most critical intersections of all three is during physical and circuit verification. IC verification configuration COST TRADEOFFS AT 28NM VS 40NM (ARM M0+) TSMC's 28nm process technology features high performance and low power consumption advantages plus seamless integration with its 28nm design ecosystem to enable faster time-to-market. The 28nm process technology supports a wide range of applications, including Central Processing Units (CPUs), graphic processors (GPUs), high-speed networking SEMIWIKI - ALL THINGS SEMICONDUCTOR!FORUMEDAIPSERVICESFOUNDRIESEFPGA / FPGASEMIWIKI FRONT PAGE Semiconductor Growth Trends. Sensor and actuator annual shipments are now about 30 billion units, connected devices have a 10% CAGR, storage trends and data traffic are growing non-linearly, these are all causing semiconductor sales to grow. The history of PHOTONICS COME INTO FOCUS: 2020 PREDICTIONS Photonics, the technology of the future, will see solid advancement in 2020. Growth rate will be impressive, with abundant applications coming into focus. Growth will be tethered by the cleverness of engineers extending electronics, and the evolution of the photonicsecosystem.
SPIE 2020 – APPLIED MATERIALS MATERIAL-ENABLED PATTERNING I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement. At IEDM Applied Materials (AMAT) tried to put together a panel across the entire semiconductorecosystem on
A BRIEF HISTORY OF GLOBALFOUNDRIES In fact, GLOBALFOUNDRIES exited 2011 as the only foundry to have shipped in the hundreds of thousands of 32nm High K Metal Gate wafers. GLOBALFOUNDRIES is a first-of-its-kind global foundry model, leveraging assets from around the world to best meet the needs of the global marketplace. The company is making substantial capitalinvestments to
EFFICIENT HANDLING OF TIMING ECOS Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancingprocess
WIRELESS CHARGING: MAGNETIC INDUCTION OR Standard wars are no stranger to technology business. In fact, they are the norm. Take, for instance, the rock star technology of 2015—wireless charging. Magnetic induction or magnetic resonance: which standard will dominate the wireless power ecosystem? That’s the crucial question while wireless charging continues to win the prominence in the technology industry, and the A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next 100 IC WAFER FABS CLOSED OR REPURPOSED SINCE 2009 Since 2009, semiconductor manufacturers around the world have closed or repurposed 100 wafer fabs, according to findings in the new report. Figure 1 shows the number of fabs closed by geographic region while Figure 2 shows a distribution of those fabs by wafer size and year. Figure 1. Japan and North America, have accounted for most of the INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely. AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
SEMIWIKI - ALL THINGS SEMICONDUCTOR!FORUMEDAIPSERVICESFOUNDRIESEFPGA / FPGASEMIWIKI FRONT PAGE Semiconductor Growth Trends. Sensor and actuator annual shipments are now about 30 billion units, connected devices have a 10% CAGR, storage trends and data traffic are growing non-linearly, these are all causing semiconductor sales to grow. The history of PHOTONICS COME INTO FOCUS: 2020 PREDICTIONS Photonics, the technology of the future, will see solid advancement in 2020. Growth rate will be impressive, with abundant applications coming into focus. Growth will be tethered by the cleverness of engineers extending electronics, and the evolution of the photonicsecosystem.
SPIE 2020 – APPLIED MATERIALS MATERIAL-ENABLED PATTERNING I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement. At IEDM Applied Materials (AMAT) tried to put together a panel across the entire semiconductorecosystem on
A BRIEF HISTORY OF GLOBALFOUNDRIES In fact, GLOBALFOUNDRIES exited 2011 as the only foundry to have shipped in the hundreds of thousands of 32nm High K Metal Gate wafers. GLOBALFOUNDRIES is a first-of-its-kind global foundry model, leveraging assets from around the world to best meet the needs of the global marketplace. The company is making substantial capitalinvestments to
EFFICIENT HANDLING OF TIMING ECOS Today, in the design of any type of system on chip (SoC), timing closure is a major problem and it only gets worse with each new, and more advanced process technology. Timing closure is closely inter-leaved with power and clock design. The complexity of achieving closure rises sharply with increasing design density and advancingprocess
WIRELESS CHARGING: MAGNETIC INDUCTION OR Standard wars are no stranger to technology business. In fact, they are the norm. Take, for instance, the rock star technology of 2015—wireless charging. Magnetic induction or magnetic resonance: which standard will dominate the wireless power ecosystem? That’s the crucial question while wireless charging continues to win the prominence in the technology industry, and the A BRIEF HISTORY OF BERKELEY DESIGN AUTOMATION Analog, mixed-signal, RF, and custom digital circuitry implemented in GHz nanometer CMOS introduce a new class of design and verification challenges that traditional transistor‑level simulators cannot adequately address. Berkeley Design Automation, Inc., (BDA) was founded in 2003 by Amit Mehrotra and Amit Narayan, UC Berkeley Ph.D. graduates within the intent of delivering a next 100 IC WAFER FABS CLOSED OR REPURPOSED SINCE 2009 Since 2009, semiconductor manufacturers around the world have closed or repurposed 100 wafer fabs, according to findings in the new report. Figure 1 shows the number of fabs closed by geographic region while Figure 2 shows a distribution of those fabs by wafer size and year. Figure 1. Japan and North America, have accounted for most of the INTEL CEO PAT GELSINGER BRINGS BACK SANJAY NATARAJAN March - 2021 - Present. Intel. Vice President, Technology & Manufacturing Group; Director, 14nm CMOS Technology Development. June 1993 - July 2015. Another good sign that Pat Gelsinger will be able to make informed decisions with people he can trust, absolutely. AN OPEN SOURCE PDK FOR 130NM PROCESS NODE The process is an older 130nm process, which is perfect for big-A/little-D work. The emphasis seems to be on logic chips. Now, this is kind of understandable, really. The whole idea is to get open source tool flows working, and when it comes to open source tool flows, analog is not too well served. It's actually an unevensituation.
PCI EXPRESS IN DEPTH In the last article i write about the Data Link Layer, in this article i'll write about the Transaction Layer. This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. The Transaction Layer uses TLPs to communicate request and completion ENABLING NEXT GENERATION SILICON IN PACKAGE PRODUCTS In early April, Gabriele Saucier kicked off Design & Reuse’s IPSoC Silicon Valley 2021 Conference. IPSoC conference as the name suggests is dedicated to semiconductor intellectual property (IP) and IP-based electronic systems. There were a number of excellent presentations at the conference. The presentations had been categorized into eight different subject matter tracks. PODCAST EPISODE 23: WHAT ARE CHIPLETS AND WHY ARE THEY Dan is joined by Krishna Settaluri, Co founder and CEO of Blue Cheetah. Krishna received his Ph.D. in electrical engineering from UC Berkeley and masters and bachelors from MIT specializing in design automation of high-speed silicon photonic links using analog generator technology. Krishna has worked at Apple, Google, Caltech and has consulted for multiple startups. LOW ENERGY SOCS WITH NEAR THRESHOLD VOLTAGE There is an important difference between low power and low energy in SOC design. Low power focuses on instantaneous power consumption. This is frequently done to deal with cooling and heat dissipation issues. Of course, it serves as a prerequisite for low energy design, which seeks to reduce overall power consumption over time. Low energy SAFETY ARCHITECTURE VERIFICATION, ISO 26262 I love to read articles about autonomous vehicles and the eventual goal of reaching level 5, Full Automation, mostly because of the daunting engineering challenges in achieving this feat and all of the technology used in the process. The auto industry already has a defined safety requirements standard called ISO 26262, and one of the SIEMENS EDA ARCHIVES Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products DIGITAL FILTERS FOR AUDIO EQUALIZER DESIGN Equalizers were initially designed and developed for movie theaters and amphitheaters or outdoor areas but now they have become ubiquitous. Equalization is essential for creating professional sound and creating real life like sound effects. Equalizers are used for controlling the energy/loudness of a particular frequency or a specific frequency range/band within an audio signal. WHAT'S THE QUICKEST WAY TO ADDRESS THE SEMICONDUCTOR What's the fastest way to increase capacity and address the semiconductor supply crunch?? We all know that more FABs are slow and expensive. Additional equipment takes many quarters to buy, build and commission (assuming you have the clean-room space) Yield improvementshelp -
SYNOPSYS EXPANDS MULTI-DIE SOLUTION LEADERSHIP WITH Complete DesignWare Die-to-Die Controller and PHY IP Solution Maximizes Performance for Efficient Inter-Die Connectivity in High-Performance Computing, AI and Networking SoCs MOUNTAIN VIEW, Calif., June 3, 2021 /PRNewswire/ -- Highlights of this Announcement: The complete DesignWare VOLTAGE DIVIDER CIRCUIT TO RUN AN LED? Hi, all Recently, I have a system running at 62V max, 54V nominal based on voltage divider formula. I wanted to have a little alert LED, so I was thinking about using 10, 1kohm resistors, and adding the LED bewteen the 9th and 10th (or 1st and 2nd, if it matters), to get atmost 6V and just a
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=> 2020-04-19 10:00:50 => 2020-04-19 17:00:50 => -Short term Covid19 impact is primarily logistics related -Longer term impact is more systemic/demand driven -Impact will wind through supply chain over several qtrs -Other issues, such as trade, remain an overhang SHORT TERM VERSUS LONG TERM IN THE SEMICONDUCTOR INDUSTRY The stocks declines over the last months seem to indicate the semiconductor industry flying off a cliff without leaving any skid marks behind. Reality may not be quite as bad as other industries such as airlines, restaurants, hotels etc; as the semiconductor industry is by nature a longer term, slower moving, inherently cyclical animal. The food chain in semiconductors is fairly long as it can take months to produce chips and the entire life cycle from design to production is usually well over a year. There is a lot of inventory and buffer in the supply chain and unlike the food industry, nothing has a short shelf life. Airline seats, hotel rooms and food all have a very definitive shelf life which goes to zero value on expiration. The semiconductor industry doesn't instantly react to short term changes in demand as those near term changes are absorbed by the supply chain buffer. There is an added "shock absorber" of pricing, which rises and falls depending upon demand and inventory levels. The semiconductor equipment industry is even more long term in nature, than the chips themselves, as new fabs and fab expansions can take years to plan and even just rolling in one piece of equipment can take several quarters from order to install. This suggests the semiconductor industry as a whole has the momentum a a very large oil tanker that takes a very long time to either accelerate or stop. NEAR TERM COVID19 ISSUES ARE PRIMARILY LOGISTICS The primary Covid19 impact to the semiconductor industry in Q1 2020 is due to logistical issues of moving people and materials around. In general, the fabs kept operating for the most part. Fabs tightened down on access by outside persons to the fabs for fear of infection. Tool shipment and installs were slowed due to transport and access issues. Tool manufacture was impacted by supply chain issues (moving sub components around) as well as people. The semiconductor manufacturing base relies on free, easy and quick movement of materials and people around the globe and was obviously impacted when that slowed. To be very clear, we have not heard of any major change in fab plans, expansions, upgrades, and technology advancement that has been impacted in a big way so far. Its not like a foundry is going to cancel its next gen process or significantly delay it. There have been reports of Samsung delaying its 3NM from 2021 to 2022 and blaming Covid19. While its clear that Covid19 is causing one to two quarter delays in equipment installs and EUV tools were cited as one issue, we think that Samsung has historically been more than overly optimistic in its projections in beating TSMC to the next gen. Samsung has missed most of its prior projections of technology readiness. When all is said and done we expect a one to two quarter overall delay or "hiccup" in the march of Moore's law, caused by primarily logistics issues related to Covid19. Longer term, demand driven issues, harder to determine We think the bigger variable, and one that is harder to project, is demand driven issues caused by Covid19. One of the reason's why this is difficult is that we are still at the very beginning of economic impact with wildly varying estimates of economic damage and impact. In general, semiconductor laden devices are "less essential" goods than food, shelter, transport & energy (though some may argue they need their smart phone more than food...). While there may be a near term spike in demand for laptops and servers due to remote work and learning, we are more concerned about reduced demand for TVs, cars, smart phones, 5G etc; as those purchases tend to be more "marginal" and vulnerable to high unemployment or business cutback in spending. Slowing of semiconductor demand will only be felt over the next several quarters and not felt in Q1 as we haven't yet seen significant demand driven issues and we have the above described supply chain buffer to delay the impact. We remain very concerned about the precarious balance of supply and demand in the commodity like memory markets and would watch those with extreme interest. We have already seen some warning signs in memory pricing. We also remain concerned about the iPhone 12 launch in the fall, which has always been timed for holiday purchases. Getting pushed out by a quarter would essentially miss the holiday window of sales. We would look to the 2008/2009 financial crisis as a bit of a guide for potential impact on semiconductors, which was significant. Except for the recent, self inflicted, memory oversupply driven down cycle, the semiconductor industry has been in a positive overall trend since 2008/2009. If we hadn't over built memory supply, we would likely have still been in the longest up cycle ever. This most recent down cycle lasted about a year and a half and most prior cycles lasted two years or more. While the short term, logistics driven impact may only last one or two quarters at most, the longer term, demand/economic driven impact will likely last one to two years. Right now the depth of the impact cannot be determined but its safe to say that the long term impact will last at least as long as the overall economic impact. SAMSUNG, INTEL & TSMC STILL SPENDING FOR NOW We continue to hear positive things about spend levels. In fact it sounds like Samsung may be planning on ramping spending in a similar fashion as they did in the prior upturn. We have also heard that Intel continues to spend to get capacity it has been short of as well as take advantage of near term spikes in demand. TSMC also continues its roll out of new technology and is remaining on track with prior plans for the most part. The bottom line is that so far, no major player in the semiconductor industry has taken their foot off the gas (for now). Between Apple, AMD, Intel, Qualcomm & Huawei among others, TSMC seems to have more than enough demand to keep it busy. Our concern here is that TSMC has broad exposure across the consumer industry and obviously more exposure to 5G roll out which could be impacted. Samsung is obviously very exposed to memory pricing but in the past has spent up and until memory prices collapsed in their face, then put the brakes on instantly. Samsung behaves in a much more binary way as it seems to be either full on the gas or full on the brakes with not a lot in between. Intel seems to be a more consistent spender, and if anything, likely too conservative as evidenced by delays and shortages of parts. Of the big three, we think Intel is least at risk to change their capital spending plans and perhaps more at risk for an up tick in spend. EARLY Q1 SIGNALS MIXED- ASML & ACLS Early signals coming out of the equipment industry are mixed. On one hand we have heard that ASML will miss expectations due to logistics issues of shipping and installing tools which is totally expected and obviously beyond their control. On the other hand we have just heard this morning that Axcelis will exceed the high end of guidance with a great quarter despite Covid19. Obviously shipping and installing scanners is much different from ion implanters and the customer base and locations are significantly different between the two companies. We think that impact on tool companies will vary depending upon customer locations and complications associated with tools. We think that Axcelis is one of the few companies that will see relatively no impact. Most will see some sort of impact. In general, materials suppliers remain a defensive bet as they will likely have the shortest term impact related only to any fab slow downs which are few. Those companies with the widest and longest supply chains that are most exposed to logistics will see the most impact, especially those with more Asia based manufacturing. THE STOCKS....BEWARE THE BOUNCE..... The stocks have bounced off a sharp decline as worst case fears seem to have abated. Initial reports are coming in better than expected and we expect will continue to come in better than worst fears. We also expect that guidance for Q2 will probably also be better than expected as much of the business pushed out of Q1 will wind up in Q2 so it will make up for any weakness and potentially look better than originally expected for many companies. As we have pointed out here, we think near term issues are primarily logistics based and by their nature, short term. As such, the stocks will discount these issues as one time, delays in an otherwise intact model. When we add the likely positive Q2 guide the stocks should see a short term "pop" We are more concerned about business one to two or more quarters out, driven by demand issues. So while we have experienced a near term "dead cat bounce" off a low bottom we are concerned that the stocks could drift down in the longer run after having a "relief rally" when investors realize that short term impact is just that. We also remain very concerned about non Covid19 issues, such as Huawei/China trade, which has all but been forgotten about by investors. The current administration could look to China as a scapegoat for Covid19 and try to punish China through Huawei or some other trade impacting mechanism. In short we may try to take advantage of a short term, quarter driven pop in the stocks but then take some money off the table as the future looks a bit more uncertain post the pop of the quarter. => Short vs Long Term Covid19 Impact=>
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Word on the virtual street is that Wave Computing is closing down. The company has reportedly let all employees go and filed for Chapter 11. As one of the many promising new companies in the field of AI, Wave Computing was founded in 2008 with the mission “to revolutionize deep learning with real-time AI solutions that scale from the edge to the datacenter.” Classified as a late stage venture, the company was founded by Dado Banatao and Pete Foley. Mr. Banatao serves as chairman of Wave Computing and is also a managing partner at Tallwood Venture Capital. Sanjai Kohli is the current CEO. Mr Kohli took the helm at Wave Computing in September 2019 from Art Swift, who held the position for only four months. The story was reported in EE Times here. The story speculated that there were performance issues with Wave’s AI dataflow processor. Did that contribute to their early exit? At present, the reasons for their exit are speculative. Wave Computing offered a broad product line. Billed as a “scalable, unified, AI platform,” Wave Computing utilized MIPS processors to offer dataflow processing technology that scaled “from the edge to the datacenter.” To make things more interesting, MIPS Technologies is owned by Wave Computing, who acquired it from Tallwood MIPS Inc., a company indirectly owned by Tallwood Venture Capital. What now happens to MIPS? In December of 2018 Wave announced the MIPS Open Initiative to expand adoption of MIPS via open (free) licensing only to close it one year later: _"Wave Computing, Inc. and its subsidiaries ('Wave') regretfully announce the closing of the MIPS Open Initiative ('MIPS Open'), and hereby give Notice of the same effective November 14, 2019 ('Effective Date')," the company's brief email to registered MIPS Open users reads. "Effective immediately, Wave will no longer be offering free downloads of MIPS Open components, including the MIPS architecture, cores, tools, IDE, simulators, FPGA packages, and/or any software code or computer hardware related thereto, licensed under any of the (i) MIPS Open Architecture License Agreement (ver. 1.0), (ii) MIPS Open Core License Agreement ver. 1.0 For the microAptiv UC Core, (iii) MIPS Open Core License Agreement ver. 1.0 For the microAptiv UP Core, and/or (iv) MIPS Open FPGA License Agreement ver. 1.0 (collectively, 'MIPS Open Components'. In addition, all MIPS Open accounts will be closed as of the Effective Date."_ Was Wave trying to do too much at once? Is narrower focus a better strategy in the emerging AI market? Again, speculation that will likely be brought into focus in the coming days and weeks. Did the current pandemic play a role? I believe those stories are yet to be told, it is likely too early for that. The AI and deep learning market is exploding with many new companies offering novel approaches. Any new market typically experiences this growth, followed by a consolidation phase. Does the news from Wave Computing signal we are already entering the consolidation phase? Time will tell. About Wave Computing Wave Computing, Inc. is revolutionizing artificial intelligence (AI) with its dataflow-based solutions. The company’s vision is to bring deep learning to customers’ data wherever it may be—from the datacenter to the edge—helping accelerate time-to-insight. Wave Computing is powering the next generation of AI by combining its dataflow architecture with its MIPS embedded RISC multithreaded CPU cores and IP. More information about Wave Computing can be found at https://wavecomp.ai . => Wave Computing and MIPS Waves Goodbye=>
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TSMC has had an incredible run since its founding in 1987 which spans most of my 36 year semiconductor career. Even in these troubled times TSMC is a shining bellwether with double digit growth expectations while the semiconductor industry will be flat or slightly down. Let’s take a close look at the TSMC Q1 2020 conference call and see what else we can learn. _“On March 18, we found one employee who tested positive for COVID-19 and immediately began receiving appropriate care. Today, this employee has recovered, is out of the hospital and is staying at home for additional quarantine. We were able to suitably trace all the other individuals who were in contact. The neighboring employees have all tested negative, while all other employees who were in contact has entered and completed the 14-day self-quarantine and now back to work. As a result of the strict preventive measures taken by TSMC, we have not seen any disruption of our fab operations so far.”_ This does not surprise me at all. Taiwan learned a very important lesson during the SARS outbreak in 2002. I remember traveling during this time and going through extra medical checks at the TPE airport. Taiwan installed medical imaging equipment that took our temperatures after we got off the planes. It is easy to remember since I had to remove my hat and got to see how big my brain is. It really is big, hat size XL. One thing you can say about TSMC is that they have built their business on experience and humility, absolutely.Dr. C.C. Wei:
_"Looking ahead to the second half of this year. Due to the market uncertainty, we adopt a more conservative view as we expect COVID-19 to continue to bring some level of disruption to the end market demand. For the whole year of 2020, we now forecast the overall semiconductor market, excluding memory growth, to be flattish to slightly decline, while foundry industry growth is expected to be high single-digit to low-teens percentage."_ In my opinion we will see a hockey-stick-like semiconductor recovery in Q4 2020. Never before have we seen the entire world united in a common cause. Never before have we seen such worldwide compassion and cooperation. COVID-19 really is a globally uniting event and it could not have come at a better time in my opinion. The world will be a much safer and more productive place in 2021 and beyond, that is my heartfelt belief. _"Now let me talk about the progress and development of 5G and HPC. With the recent disruption from COVID-19, we now expect global smartphone units to decline high single digit year-over-year in 2020. However, 5G network deployment continues and OEMs continue to prepare to launch 5G phones. We maintain our forecast for mid-teens penetration rate for 5G smartphone of the total smartphone market in 2020."_ It is understandable that the edge devices will take a pause this year but remember we are in a data driven society. With the entire world sheltering in place the amount of data generated is increasing exponentially. SemiWiki traffic alone is up 30%. Our webinar series is breaking registration and attendance records. The world wide communications infrastructure is being upgraded like never before and that means semiconductor strength. There has been a lot of fake news of late surrounding the TSMC process technology so let's get this straight from the horse's mouth (American idiom for the truth): _"Now let me talk about the ramp-up of N7, N7+ and the status of N6. In its third year of ramp, N7 continue to see very strong demand across a wide spectrum of products for mobile, HPC, IoT and automotive applications. Our N7+ is entering its second year of ramp using EUV lithography technology while paving the way for N6. Our N6 provides a clear migration path for next-wave N7 products, as the design rules are fully compatible with N7.”_ _"N6 has already entered its production and is on track for volume production before the end of this year. N6 will have one more EUV diode than N7+ and will further extend our 7-nanometer family well into the future. We expect our 7-nanometer family to continue to grow in its third year and reaffirm it will contribute more than 30% of our wafer revenue in 2020.”_ _"Now let me talk about our N5 status. N5 IS ALREADY IN VOLUME PRODUCTION WITH GOOD YIELD. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about 20% speed gain compared with N7. N5 will adopt EUV extensively. We expect a very fast and smooth ramp of N5 in the second half of this year driven by both mobile and HPC applications. We'll reiterate 5-nanometer will contribute about 10% of our wafer revenue in 2020.”_ _"N5 IS THE FOUNDRY INDUSTRY'S MOST ADVANCED SOLUTION WITH BEST PPA. WE OBSERVED A HIGHER NUMBER OF TAPEOUTS, AS COMPARED WITH N7 AT THE SAME PERIOD OF TIME. We will offer continuous enhancements to further improve the performance, power and density of our 5-nanometer technology solution into the future as well. Thus, we are confident that 5-nanometer will be another large and long-lasting node for TSMC."_ _"Finally, I will talk about our N3 status. Our N3 technology development is on track, with risk production scheduled in 2021 and target volume production in second half of 2022. We have carefully evaluated all the different technology options for our N3 technology, and our decision is to continue to use FinFET transistor structure to deliver the best technology maturity, performance and costs."_ _"Our N3 technology will be another full node stride from our N5, with about a 70% larger density gain, 10 to 15 speed gain and 25% to 30% power improvement as compared with N5. Our 3-nanometer technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced and will further extend our leadership position well into the future."_ If you have questions about this please post in the comments section and let the SemiWiki community of experts answer. Just say no to fake news.... => TSMC COVID-19 and Double Digit Growth in 2020=>
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=> 2020-04-17 06:00:49 => 2020-04-17 13:00:49 => State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation to generation. To that end, this article (second in the series on lithography resolution limits) focuses on the lithography resolution limits of arrayed feature patterning. MINIMUM PITCH RESOLUTION A lithography tool is specified by the wavelength it uses, e.g., 193 nm for ArF, 13.5 nm for EUV, as well as its numerical aperture, i.e., the power of its final optic element (lens for ArF, KrF, i-line, mirror for EUV). The formula for the _ideal _minimum pitch between two lines in an array is This result is derived from the grating equation . Basically, the minimum pitch is realized by the interference of two beams which form the maximum angles with the optical axis, whose sines differ by wavelength/pitch. The difference of sines is at most equal to twice the numerical aperture - this gives the previously stated ideal minimum pitch. Realistically, though, the difference of sines must deduct the finite angular tolerance of the beams. The actual minimum pitch should therefore be Hence, while for a wavelength of 193 nm, numerical aperture of 1.35, we ideally expect a minimum pitch of 71.5 nm, in reality it is 76 nm. Likewise for the EUV tool with nominal wavelength of 13.5 nm, numerical aperture of 0.33, the minimum pitch was recently demonstrated to be 24 nm , not the ideal 20.45 nm. For two-dimensional arrays (square arrays, rectangular arrays, triangular arrays), the patterns can be generated by crossed line arrays, with best results achieved by using an attenuated (~5%) phase-shifting effect by the mask , so the same minimum pitch resolution limit, given by equation (2), applies as for lines. In the previous article , it was noted that for a pair of features, the Rayleigh criterion (0.61 wavelength/numerical aperture) is used to determine the resolution. With arrayed features, although the pitch is already predetermined, the Rayleigh criterion applies if the array pitch is much wider than the distance set by that criterion; otherwise, it is the pitch (specifically, the half-pitch) that decides the resolution. SELF-ALIGNED PATTERNING: THE IDEAL OPPORTUNITY FOR ARRAYED FEATURES When the minimum pitch needs to go below 0.5 wavelength/numerical aperture, a single exposure is not sufficient to pattern the array. A second exposure, such as the previously described LELE (litho-etch-litho-etch) approach , can achieve half the pitch, but alignment between the two exposures cannot be guaranteed. Self-aligned patterning approaches would be better. The most commonly practiced approach is Self-Aligned Double Patterning (SADP). Its earliest comprehensive description is given in US Patent 5328810, assigned to Micron after being filed in 1992 . Figure 1 shows the first steps of basic SADP. _FIGURE 1. BASIC SADP FLOW FOLLOWING STANDARD LITHOGRAPHY._ In this drawing, it is indicated clearly that the top of the spacer is eroded during the process. Also, it is the cost-reducing preference to use photoresist as the starting feature, rather than another etched material. Figure 2 shows the completion of the SADP process. _FIGURE 2. COMPLETION OF SADP PROCESS._ The new feature pitch on the substrate is now half the original photoresist feature pitch. Hence, this allows a doubling of line density, without an additional exposure. Sharp eyes may note that the distance between features in the center is a little wider than the distance between features where the photoresist was originally located. This effect is known as "pitch walking" . This can arise from the original photoresist pattern, in combination with the spacer thickness, and the amount of spacer erosion. To manage the pitch walking the critical dimension (CD) of the starting photoresist feature must be in sync with the spacer thickness and erosion rate. Alternatively, a gapfill material may be deposited after the spacer film is deposited . This protects the exposed spacer side from erosion, but leaves extra spacer material to be removed later along with the gapfill material, as well as the starting core feature. This can be extended, however, to more than doubling feature density. For example, Samsung's US Patent 7842601 describes the double spacer approach to reducing line pitch to one-third its original value (Figure 3). This allows a 78 nm pitch (~22nm foundry node design rule) to be immediately reduced to 26 nm (<5nm foundry node design rule) in a single exposure, without using EUV. _FIGURE 3. SELF-ALIGNED TRIPLE PATTERNING (SATP) BY THE USE OF TWO SPACERS._TWO-DIMENSIONAL SELF-ALIGNED PATTERNING When the SADP process is applied to two-dimensional patterns, the possibilities expand. For example, in Figure 4, features on a square lattice are doubled in density. _FIGURE 4. TWO-DIMENSIONAL SADP ON A SQUARE LATTICE DOUBLES FEATURE DENSITY._ The central added feature is expected to round out like the original corner features of the lattice cell. Going even further, a triangular or hexagonal lattice allows feature density to be tripled. _FIGURE 5. TWO-DIMENSIONAL SATP ON A TRIANGULAR LATTICE TRIPLES FEATURE DENSITY._ The latter approach has already been used in Samsung's 20nm DRAM for the honeycomb capacitor patterning. DOUBLE SADP/SATP IN 2D? By repeating the SADP/SATP processes described above, the arrayed feature density increases in leaps and bounds. Double SADP quadruples density for line arrays and square lattices; hence, this is also referred to as self-aligned quadruple patterning (SAQP). Double SATP in two dimensions noncuples (multiplies 9x) density for triangular lattices. The feasibility of double SADP is tied to the process complexity. The complexity of double SADP is increased over that of single SADP, but having several consecutive etch steps which can be executed at the same etch station is easier to manage. The etch rates of three materials (core, spacer, substrate) are considered simultaneously in any case. On the other hand, a new EUV resist process flow may involve added deposition and treatment steps inserted (Figure 6). In particular, the new underlayer material being etched could have its own station, as it may be organic or metal-based . The underlayer benefit is expected from the effects of secondary electrons released by EUV light . _FIGURE 6. EUV RESIST PROCESS STEPS CAN STILL BE OF COMPARABLE COMPLEXITY COMPARED TO DOUBLE 2D SADP/SATP._It is quite clear that self-aligned spacer patterning is a very powerful patterning techniques for arrayed features. In upcoming articles, the use of self-aligned patterning for specific cases involving complicated array layouts will be examined.REFERENCES
https://en.wikipedia.org/wiki/Diffraction_grating https://www.imec-int.com/en/articles/imec-demonstrates-24nm-pitch-lines-with-single-exposure-euv-lithography-on-asml-s-nxe-3400b-scanner A. K-K. Wong, Optical Imaging in Projection Microlithography (SPIE, 2005), p. 87. https://www.linkedin.com/pulse/lithography-resolution-limits-paired-features-frederick-chen/ T. A. Lowrey, R. W. Chance, D. A. Cathey, US Patent 5328810, assigned to Micron, filed Nov. 25, 1992. https://www.semiconkorea.org/en/programs/STS/S4.-Plasma-Science-and-Etching-Technology/SAQP-Pitch-Walking-Improvement-Path-Finding-by-Simulation- A. E. Carlson, US Patent 8101481, assigned to the Regents of the University of California, filed Feb. 25, 2008. J-Y. Lee, J-S. Park, S-G. Woo, US Patent 7842601, assigned to Samsung, filed Apr. 20, 2006. J. M. Park et al., "20nm DRAM: A new beginning of another revolution ," IEDM 2015. J. Li et al., "A Chemical Underlayer Approach to Mitigate Shot Noise in EUV Contact Hol9e Patterning," Proc. SPIE 9051, 905117 (2014). A. De Silva et al., "High-Z metal-based underlayer to improve EUV stochastics," Proc. SPIE 11147, 111470W (2019). https://spie.org/news/6518-successes-and-frontiers-in-extreme-uv-patterning?SSO=1 => Lithography Resolution Limits - Arrayed Features=>
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=> 2020-04-16 10:00:13 => 2020-04-16 17:00:13 => Cadence recently published a position paper that details a set of enabling technologies that will be needed for product design going forward. Entitled Intelligent System Design , the piece describes the changing landscape of system design and the requirements for success. Cadence has built a branded approach to address these needs called, appropriately, the Intelligent System Design™ strategy. There is a short discussion of Cadence’s capabilities at the end of the piece, but most of the discussion is a thoughtful overview of what is changing in system design and what needs to be done to facilitate those changes. I have a few comments and observations about what Cadence is up to, but I’ll hold that until later. The vision conveyed by this position paper is far bigger than any specific product. In my view, Intelligent System Design hits home in meaningful and relevant ways on many fronts. The piece begins by setting the stage for the current wave of innovation. To effectively compete, system companies are designing their own chips and semiconductor companies are delivering software stacks along with their silicon to enable competitive differentiation. Cadence decomposes these trends in a hierarchical way, examining the requirements for design excellence, system innovation and pervasive intelligence. You really need to read the paper to get the full impact, it’s only five pages long by the way. To whet your appetite, I’ll provide a quick summary of each the three areas treated. DESIGN EXCELLENCE: The bread and butter of EDA was, for a long time, logic design, logic synthesis, place and route, timing closure, design rule check, test generation and tapeout. While those items are still necessary, there is now a lot more to deal with. Process variation, IP reuse, power and signal integrity, software interactions and complex system validation are just some of the new requirements that must all be co-optimized to achieve a successful tapeout. Cloud computing factors into the discussion as well. SYSTEM INNOVATION: Co-optimization comes into play here as well. A successful SoC must be analyzed and optimized in the context of the system for which it is intended. The PCB and the complex and potentially 2.5 or 3D package must be co-analyzed and optimized along with the chip itself. There are plenty of signal integrity challenges to addresses here. Software is also part of system innovation. To make it more interesting, design teams must develop the software for a new SoC before the SoC exists. PERVASIVE INTELLIGENCE: Deep learning is finding its way into all kinds of everyday products. The challenges to accomplish the design-in of this technology may not be as well known. Power and latency are requiring a lot of these new technologies to be resident in a more local sense, at the edge of the cloud if you will vs. in the cloud. Doing this in a cost-effective way is very challenging. It turns out EDA tools and design flows can be improved to make deep learning design easier by using deep learning in the design process itself. Something of a recursive process. THE CADENCE STRATEGY: At the end of the paper, Cadence briefly discusses their strategy to address the three areas mentioned above. You can certainly learn a lot more about their approach by visiting the Cadence website . There’s lots of new and fresh content there. In closing, I want to touch briefly on the third item, pervasive intelligence. This is an area where I believe Cadence is truly practicing what they preach. I recently posted a conversation with Cadence’s Paul Cunningham on machine learning at Cadence . In it, Paul detailed the Cadence vision of how machine learning can be used to both improve EDA algorithms and leverage learning from prior runs to make the flow better for future runs. Soon after that discussion, Cadence issued a press release about their new digital full flow . That flow uses machine learning in the ways Paul described. Having a good strategy is important. Actually, using it is also important, but often difficult. I think Cadence expresses some great visions in this new position paper, visions that can be implemented thanks to the technology available today. I’ll keep watching as this unfolds. => Cadence – Defining a Roadmap to the Future=>
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=> 2020-04-16 06:00:40 => 2020-04-16 13:00:40 => It might seem paradoxical that simulation (or equivalent dynamic methods) might be one of the best ways to run security checks. Checking security is a problem where you need to find rare corners that a hacker might exploit. In dynamic verification, no matter how much we test we know we’re not going to cover all corners, so how can it possibly be useful? Wouldn’t formal methods be much better? Dave Kelf (CMO for Breker) makes a point that security verification is inherently a _NEGATIVE_ verification problem. Unlike _POSITIVE_ testing where you’re checking that a specific scenario works as expected, in security verification you need to check all possibilities, as you ideally would in negative testing. For example, in a positive test, we would check the key can be read through the crypto block. In security, we have to ask, “is there any other way that this can be done?”. The strength of formal is that it can analyze that entire state space and find paths you had not considered. But while formal is ideal for completeness, it’s limited in scope – by the size of the state space and by the degree to which you have to abstract and decompose complex problems, leaving you to wonder what you might have overlooked in all that complexity. Formal also can’t work with software, a real problem for embedded system validation. Conversely, simulation doesn’t care – you can run whatever size system you have with whatever mixed levels you need. Nevertheless, the completeness of the graph-approach is appealing. Breker have developed a way to build a conceptually similar graph at the system level, not automatically from RTL as a formal tool would but semi-manually / semi-automatically from a series of tables describing key aspects of the SoC system architecture. Then PSS becomes a pretty logical bridge to testing complete negative intent on a high-level graph rather than conventional formal gate-level paths. Breker has an app for that. In the security TrekApp, you can define a security policy through tables, in master/slave connectivity, security/privilege options and memory address zones. An advantage in starting with these tables is that it’s easy to see what might be missing – trivially that you missed a master/slave option, you forgot to specify whether an access/privilege on the master and an access/privilege option on the slave is a valid (permitted) combination or not. Going one level deeper, you can also define, in another table, various memory regions with corresponding secure and privilege accessibilities. These definitions are essential for later dynamic tests to check that it isn’t possible, through some unapparent sequence of actions (again a negative test), to read from or write into a secure/privileged memory region from a transaction not allowed to perform those actions. Think for example of an ARM TrustZone environment in which one or more masters may at times be operating in a secure mode with a certain level of privilege, or a non-secure mode. Meanwhile slaves, some secure with low privileges, some secure with higher privileges are communicating with masters and trying to read from or write to regions in memory, each of which also have assorted privilege and secure settings. That’s a lot of combinations to worry about. Are you sure your tests are really going to cover them all? The Breker security TrekApp will map the master/slave, secure/privilege and memory region tables into the Trek internal format, then build a graph – in effect a system-level state graph – which can generate tests for all possible transactions across that graph. Their test suite synthesis will then map that to realized sequences of tests, which you can then plug into your UVM testbench or software driven SoC test. A comprehensive sequence of tests that can cover all paths through the graph, including those you might not consider but a hacker may attempt. That looks like a pretty valuable capability to me. You can learn more about the security TrekApp HERE. => Breker Tips a Hat to Formal Graphs in PSS Security Verification=>
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=> 2020-04-15 10:00:54 => 2020-04-15 17:00:54 => _How can ultra-wideband done right do more with less energy_ In the previous part , we discussed how the time-frequency duality can be used to reduce the latency. When you compress in time a wireless transmission, you reduce the time it takes to hop from a transmitter to a receiver. Another very interesting capability enabled by the time-frequency duality is the possibility to reduce the power consumption, to a level never seen before. In a world where everything goes wireless and all devices are required to be remotely controlled, the importance of power consumption is growing significantly. In a simple sensor node composed of four parts (sensor, microcontroller, PMU and transceiver), the wireless transceiver is the main contributor to the total power consumption by a large margin. Indeed, the percentage of the power used for the wireless function can exceed 90% of total power consumption. Power consumption of wireless headsets, game controllers, and computer keyboards and mice is dominated by the wireless transceiver. Power reduction has been driving the development wireless chips over the last 15 years. After years of development, BLE was ratified in 2006 to address the power consumption of Bluetooth. More recently, Bluetooth 5.2 added features to reduce consumption for different applications, including audio. However, these modifications are mostly incremental. Fundamentally, the reduction in power consumption is physically limited by the architecture; a carrier-based transceiver will always require a significant amount of power to start, stabilize and maintain its RF oscillator. After two decades of optimization, Bluetooth has reached its point of diminishing return. This is true for all narrowband technologies: gaining an order of magnitude requires a new paradigm in wireless transmission. Here’s why: THE NARROWBAND PENALTY In the chart above, you can see the two significant power penalties inherent in all narrowband radio architectures like Bluetooth:*
Crystal oscillator overhead (lower left) cripples low data rate performance: Bluetooth uses a ~20 MHz crystal oscillator, which requires a few milliwatts to power up and stabilize. UWB radios, like the one developed by SPARK Microsystems , can operate using impulses that don’t require a high frequency crystal oscillator and can be designed to operate with a low timing power consumption overhead.*
Carrier overhead (upper middle) penalizes high data rate performance: Transmitting a large amount of data over a narrow bandwidth channel such as that used in Bluetooth radios requires lots of time and power, as explained in part 4. Large amounts of data can be transmitted far more quickly when spread across a wide bandwidth, keeping the transmitter on for a much shorter duration and reducing power consumption significantly. This means for the same amount of consumed power, UWB can transmit much more data. (far upper right) HOW UWB AVOIDS THE NARROWBAND PENALTIES If you start with a blank page to design a short range (50-100m) wireless protocol that minimizes power consumption and latency and maximizes data rate, you would probably go through this thought process:*
First, minimize the time the transmitter and the receiver are powered on. To do that, each symbol should be as short as possible. From the time-frequency duality we know that a signal that is short in time has a wide bandwidth, so the solution will utilize wideband communications, hence the choice of the unlicensed UWB spectrum.*
Second, ensure that the transmitter and receiver can be started and shutdown as quickly as possible. This makes it difficult to use transceivers that use traditional high accuracy RF oscillators. The optimal architecture to minimize power consumption is the use of an UWB impulse radio that forgoes the need for an RF carrier per se. As you can see from data on the previous graph, that approach delivers the lowest possible power profile for short range communications. This is the approach SPARK Microsystems has taken for its UWB transceivers.UWB’S ADVANTAGES
Because UWB does not use a high-frequency carrier oscillator, UWB transceivers can be turned on very quickly and transmit a far higher data rate than a narrowband radio for a given power level. This, coupled with the low latency described in Part 4, makes UWB an ideal solution for the next generation of low-power wireless applications. WHY DID NARROWBAND PREVAIL IN THE 1920’S? Although ships were required to install spark gap radios after the Titanic disaster, as discussed in part 1, wideband technology of the time had two major drawbacks:*
They were extremely noisy, with poor frequency control. Transmission had to stop to enable reception on nearby frequencies. Interference was thus a big problem.*
They could not be easily modulated to handle voice or other higher data rate communications By the 1920’s, vacuum tube technology and superheterodyne circuits enabled narrowband radios to take over rapidly escalating demand for voice and other communications. In the final part of this series, we will summarize how military and commercial technology developments, along with worldwide spectrum allocations, have created a unique opportunity for UWB to dominate short range communications in the 2020’s and beyond. ABOUT FREDERIC NABKI Dr. Frederic Nabki is cofounder and CTO of SPARK Microsystems , a wireless start-up bringing a new ultra low-power and low-latency UWB wireless connectivity technology to the market. He directs the technological innovations that SPARK Microsystems is introducing to market. He has 17 years of experience in research and development of RFICs and MEMS. He obtained his Ph.D. in Electrical Engineering from McGill University in 2010. Dr. Nabki has contributed to setting the direction of the technological roadmap for start-up companies, coordinated the development of advanced technologies and participated in product development efforts. His technical expertise includes analog, RF, and mixed-signal integrated circuits and MEMS sensors and actuators. He is a professor of electrical engineering at the École de Technologie Supérieure in Montreal, Canada. He has published several scientific publications, and he holds multiple patents on novel devices and technologies touching on microsystems and integrated circuits. ABOUT DOMINIC DESLANDES Dr. Dominic Deslandes is cofounder and CSO of SPARK Microsystems , a wireless start-up bringing a new ultra low-power and low-latency UWB wireless connectivity technology to the market. He leads SPARK Microsystems’s long-term technology vision. Dominic has 20 years of experience in the design of RF systems. In the course of his career, he managed several research and development projects in the field of antenna design, RF system integration and interconnections, sensor networks and UWB communication systems. He has collaborated with several companies to develop innovative solutions for microwave sub-systems. Dr. Deslandes holds a doctorate in electrical engineering and a Master of Science in electrical engineering for Ecole Polytechnique of Montreal, where his research focused on high frequency system integration. He is a professor of electrical engineering at the École de Technologie Supérieure in Montreal, Canada. => The Story of Ultra-WideBand – Part 5: Low power is gold=>
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=> 2020-04-15 06:00:53 => 2020-04-15 13:00:53 => TinyML is kind of a whimsical term. It turns out to be a label for a very serious and large segment of AI and machine learning – the deployment of machine learning on actual end user devices (the extreme edge) at very low power. There’s even an industry group focused on the topic. I had the opportunity to preview a compelling webinar about TinyML. A lot of these topics were explained very clearly, with some significant breakthroughs detailed as well. The webinar will be broadcast on APRIL 21, 2020 AT 10AM PACIFIC TIME. I strongly urge you to register for Artificial Intelligence in Micro-Watts: How to Make TinyML a Reality here. The webinar is presented by Eta Compute . The company was founded in 2015 and focuses on ultra-low power microcontroller and SoC technology for IoT. The webinar presentation is given by Semir Haddad, senior director of product marketing at Eta Compute. Semir is a passionate and credible speaker on the topic of AI and machine learning, with 20 years of experience in the field of microprocessors and microcontrollers. Semir also holds four patents. In his own words, “all of my career I have been focused on bringing intelligence in embedded devices.” The webinar focuses on the deployment of deep learning algorithms at the extreme edge of IoT and presents an innovative new chip from Eta Compute for this market, the ECM3532. Given the latency, power, privacy and cost issues of moving data to the cloud, there is strong momentum toward bringing deep learning closer to the end application. I’m sure you’ve seen many discussions about AI at the edge. This webinar takes it a step further, to the extreme edge. Think of deep learning in products such as thermostats, washing machines, health monitors, hearing aids, asset tracking technology and industrial networks to name a few. The figure below does a good job portraying the spectrum of power and performance for the various processing nodes of IoT. A power budget of ~1MW is daunting and this is where the innovation of Eta Compute and the ECM3532 shine. Semir does a great job explaining what the challenges of ultra-low power and ultra-low cost deployment for deep learning are. I encourage you to attend the webinar to get the full story. Here is a brief summary to whet your appetite. Traditional MCUs and MPUs operate in a synchronous nature. Getting timing closed on a design like this over process, voltage and temperature conditions is quite challenging. As power consumption is proportional to the square of the operating voltage, lowering the voltage can reduce power. But this approach will reduce operating frequency to allow timing closure. An impossible balancing act to get to low power and high performance. Dynamic voltage and frequency scaling (DVFS) is one way to address this problem, but the impacts of approaches like this across the chip continue to make it difficult to achieve the optimal balance of power and performance for a synchronous design. Eta Compute approaches the problem in a different way with continuous voltage and frequency scaling (CVFS). They are the inventor of this technology, with seven patents for both hardware and software, with more patents in the pipeline. The key innovation here is a major re-design of the processor architecture to allow self-timed performance on a device-by-device basis. This allows easier timing closure and results in higher performance for the same voltage when compared to traditional approaches. Their approach also allows frequency and voltage to be controlled by software. For example, if the user sets the frequency for a particular workload, the voltage will adjust automatically. THE BOTTOM LINE IS A 10X IMPROVEMENT IN ENERGY EFFICIENCY, which is a game changer. Eta Compute also examined what was needed for TinyML from an architectural point of view. It turns out that DSPs are better at some parts of deep learning for IoT and CPUs are better for other parts. So, the ECM3532 supports a dual core architecture, with both Arm M3 and dual MAC DSPs on board that can operate at independent frequencies. There is a lot more in-depth discussion on this and other topics during the webinar. I will leave you with some information on availability. An ASIC version of the architecture, the ECM3531 and an evaluation board is available now. Samples of the full ECM3532 AI platform and evaluation board will be available in April 2020 with full production in May 2020. Eta Compute is also working on a software environment (called the TENSAI platform) to help move your deep learning application from the bench to the ECM3532 with full access to all the optimization technologies. There is a lot more eye-popping power and performance information presented during the webinar. I highly recommend you REGISTER AND CATCH THIS EVENT HERE . => Artificial Intelligence in Micro-Watts: How to Make TinyML a Reality=>
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=> 2020-04-14 10:00:19 => 2020-04-14 17:00:19 => How do most IC design teams organize their work during the design process? Most design teams would say that they organize their work into a project-centric view, and that at the beginning of the process use a tool for requirements management, maybe a bug tracker, or some design management tool. On the four IC designs that I worked on in the 70's and 80's, each one took a project-centric view, and there was virtually zero IP reuse going on. Let's take a closer look at some common issues that arise with a project-centric approach to SoC design.SCALABILITY
A team starts out on a new SoC and then someone in the CAD groups sets up a new project in each of their tools, like: * Requirements management* Bug tracking
* Design Management Most electronic products tend to reuse cells, blocks, modules and sub-systems from previous products, but how does a project-centric flow account for any of this IP reuse? Any dependencies in these IP blocks are not really handled with point tools that basically silo design data. Each new project then gets a new DM server instance, and who is going to maintain these servers for years or even decades? If your company has four concurrent projects going on, then who is tracking what is commonly used between each of the projects, when all of the tools are setup per project? If your tools only understand the scope of what's inside each Project, then there's a gap of knowing what happens if a common cell, block, module or sub-system (IP) is changed or a bug is fixed, creating a new version.COLLABORATION
Common IP blocks being used within multiple projects makes collaborating a challenge, because each project has their own permission settings, as individual servers are setup per project. Who wants to stop an ongoing project to request access to all IP blocks being used?TRACEABILITY
When purchasing design or verification IP you have to sign a license agreement with each vendor, and these vendors want to track how many instances of their valuable IP is being used to ensure that the agreement terms are being met. You really want to know how all IP is being used, across all projects, not just within one project. Countries have laws in place regarding how silicon IP is being used or exported, and for American companies the U.S. Department of State has defined the International Traffic in Arms Regulations (ITAR). Your company needs to know how each IP block complies with ITAR or other local requirements. If a bug is found inside some IP block, and that block is re-used in multiple projects, then how does each project team hear about the bug fix? IP-CENTRIC DESIGN PROCESS There is an alternative approach to a project-centric design process with its challenges, and that is to use an IP-centric design process. Instead of each project being a silo of design data, each project can be treated as an IP block as part of a connected hierarchy of other IP blocks as shown below: With this IP-centric approach each Project continues to have its own permissions and DM backend as desired. IP metadata goes along with each IP block, so that all users of an IP block have all the info they need when reusing. Even dependencies from bug tracking tools and requirements tools are integrated into this IP-centric view. Scaling works well because there's a centralized server that can be quickly update once there's an IP update, then its effects are seen in all projects. This is the approach that METHODICS has taken with Percipient , their IP Lifecycle Management (IPLM) tool. Shown below are four projects being managed with the Percipient central server. Your company can even follow a Zero-Downtime upgrade policy while using a central server approach. When a bug is found for an IP block in Project A, then an engineer would file a bug report under Project A. Engineers on Project B and C would then note that a new bug was just filed on the re-used IP block.SUMMARY
Times have changed, and IC designs are getting larger every day, so the approach that your company and teams take makes a difference. The project-centric approach worked OK for small designs with little IP reuse, however for today's SoC projects you'd be better served with the IP-centric approach being offered by Methodics. I like how they've integrated with other bug tracking and DM tools, so you don't have to ask your CAD group to customize lots of point tools to play well together. Here's a final view of how Percipient provides several useful management features. To read the complete 10 page White Paper, browse here .RELATED BLOGS
*
Avoiding Fines for Semiconductor IP Leakage*
Webinar Recap: IP Security Threats in your SoC*
Workflow Automation Applied to IP Lifecycle Management*
Achieving Functional Safety through a Certified Flow => Project-centric Design Process, or IP-centric=>
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=> 2020-04-14 06:00:17 => 2020-04-14 13:00:17 => This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea. We’re getting a lot of hits on these blogs but would like really like to get feedback also. I’ve setup a link for you to post _ANONYMOUSLY_ and to review posts from others. Click here to comment . Feedback will be accepted for one week from this posting.THE INNOVATION
Our next pick is Metamorphic Relations for Detection of Performance Anomalies . The paper was presented at the 2019 IEEE/ACM International Workshop on Metamorphic Testing. The authors are from Adobe, the University of Wollongong, Australia and the Swinburne University of Technology, Australia. Metamorphic testing (MT) is a broad principle to get around the _ORACLE_ problem – not having a golden reference to compare for correctness. Instead it checks relationships expected to hold between related tests. Maybe for a distribution in runtimes, or correspondence between two software runs with code changes, or many other examples . The authors applied the principle to test performance in software called a tag manager. Tags are slivers of JavaScript inserted in a web page to collect information from page views. Consumer-focused companies may have 50+ tags on a page, a maintenance headache. Tag managers allow marketing to quickly update these without web expertise, at the expense of some added page load time. The authors tested load times for an Adobe tag manager. Since multiple factors influence load, they expected a distribution. The metamorphic relationship they chose was that load times with tagging should be shifted (by tag support overhead) from load times without tagging, but that distributions should otherwise be similar. The relationship held in most cases except one where the managed distribution became bimodal. This they tracked to a race condition between different elements of the code. Depending on execution order a certain function would or would not run, causing the bimodal distribution. This was a bug; the function should have run in either case. When fixed, the distribution again became unimodal. The authors also describe how they automated this testing.PAUL
I like this. I see it as a way to do statistical anomaly-based QA. You compare a lot of runs, looking at distributions to spot bugs. I see a lot of applications: anything performance-related, heuristic-based, machine-learning-based will be naturally statistical. Distribution analyses can then reveal more complex issues than pass/fail analyses. MT gives us tools to find those kinds of problem. For functional verification, this is a new class of coverage we can plan and track alongside traditional static and dynamic coverage metrics. I’m excited by the idea that a whole new family of chip verification tools could be envisioned around MT, and I welcome any startups in this space who want to reach out to me. The main contribution in this paper assumes, given some performance metric with random noise, you’re going to have a distribution. Mu/sigma alone don’t fully classify the distribution. If the it’s multi-modal, maybe there’s a race? Now I'm looking to distribution modality to detect things like race conditions. That’s great and got me thinking how we might use this in our QA. They discuss mechanics to automate detecting bi-modality, but then raise another possibility – using machine learning to check for changes between distributions. Mathematical characterization may not be as general as training a neural network to detect anomalies between different sets of runs. Similar to what credit card companies do in analyzing your spending patterns. If an anomaly is detected, maybe you’ve been hacked. MT could find problems sooner and at finer levels than traditional software testing. The latter will find obvious memory leaks or race conditions, but MT plus statistical analysis may probe more sensitively for problems that might otherwise be missed. Finally, the authors discuss outliers in the distribution, that these should remain similar between distributions. I’m excited to see how they develop this further, how they might detect difference in outliers and what bugs those changes might uncover. Generally, I see significant opportunity in exploiting these ideas.JIM
This is the first of the papers we’ve looked at in this series which to me is more than just a feature. This paper would definitely be worth putting money behind, trying to get to production. It looks like a product, perhaps a new class of verification tool. It might even work as a startup. It reminds me of Solido and Spice. We used similar techniques to get beyond the regular statistical distributions – they were at six sigma already, very hard to get better. They had to start doing stuff like this to go further. I heard “no-one's going to buy more, they already have spice”. Well they did buy a lot more. There is appetite out there for innovation of this kind. I’m also very interested in the security potential, especially for the DoD. Another worthy investment area.ME
As Paul says, MT is a rich vein, too rich to address in one blog. I’ll add one thought I found in this paper . We invest huge amounts of time and money in testing. For passing tests, the _ONLY_ value we get is that they didn’t fail. Can we extract more? Maybe we can through MT. => Innovation in Verification April 2020=>
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=> 2020-04-19 10:00:50 => 2020-04-19 17:00:50 => -Short term Covid19 impact is primarily logistics related -Longer term impact is more systemic/demand driven -Impact will wind through supply chain over several qtrs -Other issues, such as trade, remain an overhang SHORT TERM VERSUS LONG TERM IN THE SEMICONDUCTOR INDUSTRY The stocks declines over the last months seem to indicate the semiconductor industry flying off a cliff without leaving any skid marks behind. Reality may not be quite as bad as other industries such as airlines, restaurants, hotels etc; as the semiconductor industry is by nature a longer term, slower moving, inherently cyclical animal. The food chain in semiconductors is fairly long as it can take months to produce chips and the entire life cycle from design to production is usually well over a year. There is a lot of inventory and buffer in the supply chain and unlike the food industry, nothing has a short shelf life. Airline seats, hotel rooms and food all have a very definitive shelf life which goes to zero value on expiration. The semiconductor industry doesn't instantly react to short term changes in demand as those near term changes are absorbed by the supply chain buffer. There is an added "shock absorber" of pricing, which rises and falls depending upon demand and inventory levels. The semiconductor equipment industry is even more long term in nature, than the chips themselves, as new fabs and fab expansions can take years to plan and even just rolling in one piece of equipment can take several quarters from order to install. This suggests the semiconductor industry as a whole has the momentum a a very large oil tanker that takes a very long time to either accelerate or stop. NEAR TERM COVID19 ISSUES ARE PRIMARILY LOGISTICS The primary Covid19 impact to the semiconductor industry in Q1 2020 is due to logistical issues of moving people and materials around. In general, the fabs kept operating for the most part. Fabs tightened down on access by outside persons to the fabs for fear of infection. Tool shipment and installs were slowed due to transport and access issues. Tool manufacture was impacted by supply chain issues (moving sub components around) as well as people. The semiconductor manufacturing base relies on free, easy and quick movement of materials and people around the globe and was obviously impacted when that slowed. To be very clear, we have not heard of any major change in fab plans, expansions, upgrades, and technology advancement that has been impacted in a big way so far. Its not like a foundry is going to cancel its next gen process or significantly delay it. There have been reports of Samsung delaying its 3NM from 2021 to 2022 and blaming Covid19. While its clear that Covid19 is causing one to two quarter delays in equipment installs and EUV tools were cited as one issue, we think that Samsung has historically been more than overly optimistic in its projections in beating TSMC to the next gen. Samsung has missed most of its prior projections of technology readiness. When all is said and done we expect a one to two quarter overall delay or "hiccup" in the march of Moore's law, caused by primarily logistics issues related to Covid19. Longer term, demand driven issues, harder to determine We think the bigger variable, and one that is harder to project, is demand driven issues caused by Covid19. One of the reason's why this is difficult is that we are still at the very beginning of economic impact with wildly varying estimates of economic damage and impact. In general, semiconductor laden devices are "less essential" goods than food, shelter, transport & energy (though some may argue they need their smart phone more than food...). While there may be a near term spike in demand for laptops and servers due to remote work and learning, we are more concerned about reduced demand for TVs, cars, smart phones, 5G etc; as those purchases tend to be more "marginal" and vulnerable to high unemployment or business cutback in spending. Slowing of semiconductor demand will only be felt over the next several quarters and not felt in Q1 as we haven't yet seen significant demand driven issues and we have the above described supply chain buffer to delay the impact. We remain very concerned about the precarious balance of supply and demand in the commodity like memory markets and would watch those with extreme interest. We have already seen some warning signs in memory pricing. We also remain concerned about the iPhone 12 launch in the fall, which has always been timed for holiday purchases. Getting pushed out by a quarter would essentially miss the holiday window of sales. We would look to the 2008/2009 financial crisis as a bit of a guide for potential impact on semiconductors, which was significant. Except for the recent, self inflicted, memory oversupply driven down cycle, the semiconductor industry has been in a positive overall trend since 2008/2009. If we hadn't over built memory supply, we would likely have still been in the longest up cycle ever. This most recent down cycle lasted about a year and a half and most prior cycles lasted two years or more. While the short term, logistics driven impact may only last one or two quarters at most, the longer term, demand/economic driven impact will likely last one to two years. Right now the depth of the impact cannot be determined but its safe to say that the long term impact will last at least as long as the overall economic impact. SAMSUNG, INTEL & TSMC STILL SPENDING FOR NOW We continue to hear positive things about spend levels. In fact it sounds like Samsung may be planning on ramping spending in a similar fashion as they did in the prior upturn. We have also heard that Intel continues to spend to get capacity it has been short of as well as take advantage of near term spikes in demand. TSMC also continues its roll out of new technology and is remaining on track with prior plans for the most part. The bottom line is that so far, no major player in the semiconductor industry has taken their foot off the gas (for now). Between Apple, AMD, Intel, Qualcomm & Huawei among others, TSMC seems to have more than enough demand to keep it busy. Our concern here is that TSMC has broad exposure across the consumer industry and obviously more exposure to 5G roll out which could be impacted. Samsung is obviously very exposed to memory pricing but in the past has spent up and until memory prices collapsed in their face, then put the brakes on instantly. Samsung behaves in a much more binary way as it seems to be either full on the gas or full on the brakes with not a lot in between. Intel seems to be a more consistent spender, and if anything, likely too conservative as evidenced by delays and shortages of parts. Of the big three, we think Intel is least at risk to change their capital spending plans and perhaps more at risk for an up tick in spend. EARLY Q1 SIGNALS MIXED- ASML & ACLS Early signals coming out of the equipment industry are mixed. On one hand we have heard that ASML will miss expectations due to logistics issues of shipping and installing tools which is totally expected and obviously beyond their control. On the other hand we have just heard this morning that Axcelis will exceed the high end of guidance with a great quarter despite Covid19. Obviously shipping and installing scanners is much different from ion implanters and the customer base and locations are significantly different between the two companies. We think that impact on tool companies will vary depending upon customer locations and complications associated with tools. We think that Axcelis is one of the few companies that will see relatively no impact. Most will see some sort of impact. In general, materials suppliers remain a defensive bet as they will likely have the shortest term impact related only to any fab slow downs which are few. Those companies with the widest and longest supply chains that are most exposed to logistics will see the most impact, especially those with more Asia based manufacturing. THE STOCKS....BEWARE THE BOUNCE..... The stocks have bounced off a sharp decline as worst case fears seem to have abated. Initial reports are coming in better than expected and we expect will continue to come in better than worst fears. We also expect that guidance for Q2 will probably also be better than expected as much of the business pushed out of Q1 will wind up in Q2 so it will make up for any weakness and potentially look better than originally expected for many companies. As we have pointed out here, we think near term issues are primarily logistics based and by their nature, short term. As such, the stocks will discount these issues as one time, delays in an otherwise intact model. When we add the likely positive Q2 guide the stocks should see a short term "pop" We are more concerned about business one to two or more quarters out, driven by demand issues. So while we have experienced a near term "dead cat bounce" off a low bottom we are concerned that the stocks could drift down in the longer run after having a "relief rally" when investors realize that short term impact is just that. We also remain very concerned about non Covid19 issues, such as Huawei/China trade, which has all but been forgotten about by investors. The current administration could look to China as a scapegoat for Covid19 and try to punish China through Huawei or some other trade impacting mechanism. In short we may try to take advantage of a short term, quarter driven pop in the stocks but then take some money off the table as the future looks a bit more uncertain post the pop of the quarter. => Short vs Long Term Covid19 Impact=>
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Posted on April 19, 2020April 19, 2020 SHORT VS LONG TERM COVID19 IMPACT Short vs Long Term Covid19 Impact by Robert Maire on 04-19-2020 at 10:00 amView Profile
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Semiconductor Services -Short term Covid19 impact is primarily logistics related -Longer term impact is more systemic/demand driven -Impact will wind through supply chain over several qtrs -Other issues, such as trade, remain an overhang SHORT TERM VERSUS LONG TERM IN THE SEMICONDUCTOR INDUSTRY The stocks declines over the last months seem to indicate… Read More ------------------------- Posted on April 19, 2020April 19, 2020 WAVE COMPUTING AND MIPS WAVES GOODBYE Wave Computing and MIPS Waves Goodbye by Mike Gianfagna on 04-19-2020 at 8:00 amView Profile
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Word on the virtual street is that Wave Computing is closing down. The company has reportedly let all employees go and filed for Chapter 11. As one of the many promising new companies in the field of AI, Wave Computing was founded in 2008 with the mission “to revolutionize deep learning with real-time AI solutions that scale from the… ReadMore
------------------------- Posted on April 17, 2020April 18, 2020 TSMC COVID-19 AND DOUBLE DIGIT GROWTH IN 2020 TSMC COVID-19 and Double Digit Growth in 2020 by Daniel Nenni on 04-17-2020 at 10:00 amView Profile
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TSMC has had an incredible run since its founding in 1987 which spans most of my 36 year semiconductor career. Even in these troubled times TSMC is a shining bellwether with double digit growth expectations while the semiconductor industry will be flat or slightly down. Let’s take a close look at the TSMC Q1 2020 conference call and…Read More
------------------------- Posted on April 17, 2020April 17, 2020 LITHOGRAPHY RESOLUTION LIMITS – ARRAYED FEATURES Lithography Resolution Limits – Arrayed Features by Fred Chen on 04-17-2020 at 6:00 amView Profile
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State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More ------------------------- Posted on April 16, 2020April 16, 2020 CADENCE – DEFINING A ROADMAP TO THE FUTURE Cadence – Defining a Roadmap to the Future by Mike Gianfagna on 04-16-2020 at 10:00 amView Profile
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Cadence recently published a position paper that details a set of enabling technologies that will be needed for product design going forward. Entitled Intelligent System Design,
the piece describes the changing landscape of system design and the requirements for success. Cadence has built a branded approach to address these… Read More ------------------------- Posted on April 16, 2020April 12, 2020 BREKER TIPS A HAT TO FORMAL GRAPHS IN PSS SECURITY VERIFICATION Breker Tips a Hat to Formal Graphs in PSS Security Verification by Bernard Murphy on 04-16-2020 at 6:00 amView Profile
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It might seem paradoxical that simulation (or equivalent dynamic methods) might be one of the best ways to run security checks. Checking security is a problem where you need to find rare corners that a hacker might exploit. In dynamic verification, no matter how much we test we know we’re not going to cover all corners, so howcan it… Read More
------------------------- Posted on April 15, 2020April 15, 2020 THE STORY OF ULTRA-WIDEBAND – PART 5: LOW POWER IS GOLD The Story of Ultra-WideBand – Part 5: Low power is gold by Frederic Nabki & Dominic Deslandes on 04-15-2020 at 10:00 amView Profile
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_How can ultra-wideband done right do more with less energy_ In the previous part , we discussed how the time-frequency duality can be used to reduce the latency. When you compress in time a wireless transmission, you reduce the time it takes to hop from a transmitter to a receiver. Another very interesting capability enabled by the… Read More ------------------------- Posted on April 15, 2020April 15, 2020 ARTIFICIAL INTELLIGENCE IN MICRO-WATTS: HOW TO MAKE TINYML A REALITY Artificial Intelligence in Micro-Watts: How to Make TinyML a Reality by Mike Gianfagna on 04-15-2020 at 6:00 amView Profile
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TinyML is kind of a whimsical term. It turns out to be a label for a very serious and large segment of AI and machine learning – the deployment of machine learning on actual end user devices (the extreme edge) at very low power. There’s even an industry group focused on the topic. I had the opportunity to preview a compelling webinar about… Read More ------------------------- Posted on April 14, 2020April 13, 2020 PROJECT-CENTRIC DESIGN PROCESS, OR IP-CENTRIC Project-centric Design Process, or IP-centric by Daniel Payne on 04-14-2020 at 10:00 amView Profile
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Categories: EDA , Methodics How do most IC design teams organize their work during the designprocess?
Most design teams would say that they organize their work into a project-centric view, and that at the beginning of the process use a tool for requirements management, maybe a bug tracker, or some design management tool. On the four IC designs that I worked … Read More ------------------------- Posted on April 14, 2020April 13, 2020 INNOVATION IN VERIFICATION APRIL 2020 Innovation in Verification April 2020 by Bernard Murphy on 04-14-2020 at 6:00 amView Profile
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Categories: Cadence , EDA This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further buildon that idea.
We’re getting a lot of hits on these blogs but would like really like to get feedback also. I’ve setup a link for you to post… ReadMore
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